1. Field of the Invention
The present invention relates to semiconductor memory devices, nonvolatile memory devices and magnetic memory devices, and more particularly to a semiconductor memory device, a nonvolatile memory device and a magnetic memory device of high reliability.
2. Description of the Background Art
In recent years, a magnetic random access memory (MRAM) has been studied as a next-generation semiconductor memory device.
For example, “Nonvolatile RAM based on Magnetic Tunnel Junction Elements”, ISSCC Digest of Technical Papers, February 2000, pp. 130-131, discloses a memory cell of an MRAM that is a so-called “1 MTJ+1 transistor type” nonvolatile memory device formed of a tunneling magneto-resistive (TMR) element including a magnetic tunnel junction (MTJ) and a transistor (see FIG. 7.3.1 of the paper). The memory cell of the MRAM disclosed in the paper as an example of the magnetic memory device or nonvolatile memory device has a digit line arranged beneath the TMR element with an insulating layer interposed therebetween. A bit line is arranged in contact with an upper surface of the TMR element. Currents are passed through the digit line and the bit line to generate a magnetic field, which is used to change a magnetization direction of a ferromagnetic layer as a free layer constituting the MTJ of the TMR element, thereby allowing data rewriting in the corresponding memory cell.
In the case where a memory cell portion including the memory cell of the MRAM as described above is to be formed additionally on a semiconductor substrate on which a logic portion including a control circuit and others has been formed, it would be possible to form conductor layers such as the digit line and the bit line in the memory cell portion with the same layers as interconnection layers in the logic portion. The interconnection layers in the logic portion, however, have a distance therebetween (thickness of an interlayer insulating film located between two of the interconnection layers stacked one on another) that is determined taking account of parasitic capacitance and others of the interconnection structure in the logic portion. Thus, forming the digit line and the bit line in the memory cell portion simply with the same layers as the interconnection layers in the logic portion would make the interval between the digit line and the TMR element formed beneath the bit line (thickness of an interlayer insulating film between the TMR element and the digit line) unnecessarily large from the standpoint of the characteristics required for the memory cell.
With such an unnecessarily large interval (distance) between the digit line and the TMR element, the magnetic field generated by the current passed through the digit line and applied to the TMR element would be insufficient in strength, with which the magnetization direction of the free layer as described above would not be changed accurately (hindering data rewriting), thereby degrading reliability.